Methods of forming integrated circuit devices frequently include techniques to form multiple layers of metallization on an integrated circuit substrate. These techniques may also include damascene and other techniques to form metal interconnects that extend between the multiple layer of metallization. Some of these techniques to form metal interconnects, which utilize electroless plating techniques, are disclosed in U.S. Pat. No. 6,380,065 to Komai et al., entitled “Interconnection Structure and Fabrication Process Therefor,” and U.S. Pat. No. 6,395,627 to Hoshino et al., entitled “Semiconductor Device, A Buried Wiring Structure and Process for Fabricating the Same.” In particular, the '065 patent to Komai et al. discloses reducing an aspect ratio of a contact hole by depositing copper into the contact hole using an electroless plating method and a lower copper interconnect as a catalyst. The '627 patent to Hoshino et al. discloses using electroless plating to completely fill a via hole with a metal plug. Additional techniques to form metal interconnects utilize chemical mechanical polishing techniques and metal seed layers to define dual damascene patterns. One of these techniques is disclosed by Korean Patent Publication No. 20050056383 to Min, entitled “Method of Forming Metal Line of Semiconductor Device Without Protrusion of Metal Plating Layer.”